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                                <h1 id="&#x786C;&#x4EF6;&#x90E8;&#x5206;&#x8BF4;&#x660E;">&#x786C;&#x4EF6;&#x90E8;&#x5206;&#x8BF4;&#x660E;</h1>
<center><img src="../img/lab2/01.png" alt="02-26" style="zoom:80%;"></center><center style="color:#0" ;="">&#x672C;&#x5B9E;&#x9A8C;&#x4E2D;&#x5B9E;&#x73B0;&#x7684;&#x786C;&#x4EF6;&#x7ED3;&#x6784;</center> 

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<div class="panel panel-danger"><div class="panel-heading"><h5 class="panel-title" id="bram-"><i class="fa fa-bullhorn"></i> BRAM ?</h5></div><div class="panel-body"><p>&#x672C;&#x5B9E;&#x9A8C;&#x4E2D;&#x642D;&#x5EFA;&#x7684; BRAM &#x7528;&#x4E8E;&#x5B58;&#x653E;&#x7A0B;&#x5E8F;&#x4EE3;&#x7801;, &#x6839;&#x636E; Cortex-M0 &#x4F53;&#x7CFB;&#x63A8;&#x8350;, &#x5176;&#x5730;&#x5740;&#x8303;&#x56F4;&#x8BBE;&#x4E3A; 0x00000000-0x0000ffff.</p></div></div>
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<div class="panel panel-info"><div class="panel-heading"><h5 class="panel-title" id="&#x6211;&#x9700;&#x8981;&#x505A;&#x4EC0;&#x4E48;-"><i class="fa fa-comment"></i> &#x6211;&#x9700;&#x8981;&#x505A;&#x4EC0;&#x4E48; ?</h5></div><div class="panel-body"><p>&#x5728;&#x5C0F;&#x8282;&#x4E2D;, &#x6211;&#x4EEC;&#x5DF2;&#x7ECF;&#x4E3A;&#x4F60;&#x51C6;&#x5907;&#x597D;&#x4E86;&#x5927;&#x90E8;&#x5206;&#x7684;&#x786C;&#x4EF6;&#x8BBE;&#x8BA1;&#x4EE3;&#x7801;, &#x4F60;&#x53EA;&#x9700;&#x8981;&#x505A;&#x4E00;&#x4E9B;&#x4FEE;&#x6539;&#x5B8C;&#x5584;:</p><ol>
<li>&#x4FEE;&#x6539;&#x603B;&#x7EBF;&#x6269;&#x5C55;&#x6A21;&#x5757; &quot;/Task2/rtl/AHBlite_Decoder.v&quot; &#x4E2D;&#x7684;&#x8BD1;&#x7801;&#x6A21;&#x5757;&#x4EE3;&#x7801;, &#x6839;&#x636E; BRAM &#x5730;&#x5740;&#x8303;&#x56F4; 0x00000000-0x0000ffff &#x5B8C;&#x5584;&#x5BF9;&#x5E94;&#x7684;&#x8BD1;&#x7801;&#x903B;&#x8F91;. </li>
<li>&#x4FEE;&#x6539;&#x9876;&#x5C42;&#x6587;&#x4EF6; &quot;/Task2/rtl/CortexM0_SoC.v&quot; &#x4EE3;&#x7801;, &#x8FDE;&#x63A5; BRAM &#x63A5;&#x53E3; (AHBlite_Block_RAM) &#x4E0E;&#x603B;&#x7EBF;&#x4E92;&#x8FDE;&#x6A21;&#x5757; (AHBlite_Interconnect). </li>
</ol><p>&#x5982;&#x679C;&#x4F60;&#x6CA1;&#x6709;&#x601D;&#x8DEF;, &#x4E0D;&#x8981;&#x614C;, &#x53EF;&#x4EE5;&#x770B;&#x770B;&#x63A5;&#x4E0B;&#x6765;&#x7684;&#x8BB2;&#x89E3;:</p></div></div>
<table>
<thead>
<tr>
<th>rtl &#x6A21;&#x5757;</th>
<th>&#x8BF4;&#x660E;</th>
</tr>
</thead>
<tbody>
<tr>
<td>cortexm0ds_logic</td>
<td>Cortex-M0 &#x5904;&#x7406;&#x5668;&#x6838;</td>
</tr>
<tr>
<td>Block_RAM</td>
<td>RTL &#x5B9E;&#x73B0;&#x7684; RAM &#x5355;&#x5143;</td>
</tr>
<tr>
<td>AHBlite_Interconnect</td>
<td>&#x603B;&#x7EBF;&#x4E92;&#x8FDE;&#x6A21;&#x5757;, &#x7528;&#x4E8E;&#x6240;&#x6709;&#x4E3B;&#x8BBE;&#x5907;&#x548C;&#x4ECE;&#x8BBE;&#x5907;&#x7684;&#x4E92;&#x8FDE;</td>
</tr>
<tr>
<td>AHBlite_Block_RAM</td>
<td>RAM &#x63A5;&#x53E3;</td>
</tr>
<tr>
<td>AHBlite_Decoder</td>
<td>&#x5730;&#x5740;&#x8BD1;&#x7801;&#x5668;, &#x662F;&#x603B;&#x7EBF;&#x4E92;&#x8FDE;&#x6A21;&#x5757;&#x7684;&#x91CD;&#x8981;&#x7EC4;&#x6210;&#x90E8;&#x5206;</td>
</tr>
<tr>
<td>AHBlite_SlaveMUX</td>
<td>MUX &#x5355;&#x5143;, &#x7528;&#x4E8E;&#x4ECE;&#x8BBE;&#x5907;&#x8FD4;&#x56DE;&#x6570;&#x636E;&#x591A;&#x8DEF;&#x9009;&#x62E9;, &#x662F;&#x603B;&#x7EBF;&#x4E92;&#x8FDE;&#x6A21;&#x5757;&#x7684;&#x91CD;&#x8981;&#x7EC4;&#x6210;&#x90E8;&#x5206;</td>
</tr>
<tr>
<td>CortexM0_SoC</td>
<td>&#x7CFB;&#x7EDF;&#x7684;&#x9876;&#x5C42;&#x6587;&#x4EF6;</td>
</tr>
</tbody>
</table>
<h5 id="cortexm0dslogic">cortexm0ds_logic</h5>
<p>&#x7531; ARM &#x5B98;&#x65B9;&#x63D0;&#x4F9B;&#x7684;&#x8BC4;&#x4F30;&#x7248; Cortex-M0, &#x53CD;&#x5411;&#x7ED3;&#x679C;, &#x4E0D;&#x8981;&#x5C1D;&#x8BD5;&#x53BB;&#x8BFB;&#x61C2;&#x5B83;.</p>
<h5 id="blockram">Block_RAM</h5>
<ul>
<li>&#x5355;&#x7AEF;&#x53E3; RAM, &#x8F93;&#x5165;&#x8F93;&#x51FA;&#x6570;&#x636E;&#x4F4D;&#x5BBD;&#x56FA;&#x5B9A;&#x4E3A; 32, &#x5B58;&#x50A8;&#x6DF1;&#x5EA6;&#x53EF;&#x8C03;&#x8282;.</li>
<li>&#x4F7F;&#x7528; Vivado &#x63D0;&#x4F9B;&#x7684; IP &#x4E5F;&#x53EF;&#x4EE5;&#x5B9E;&#x73B0; RAM, &#x4F46;&#x662F;&#x4E0D;&#x65B9;&#x4FBF;&#x8DE8;&#x5E73;&#x53F0;&#x4EFF;&#x771F;, &#x8003;&#x8651;&#x5230;&#x672C;&#x5B9E;&#x9A8C;&#x4E2D;&#x9700;&#x8981;&#x7684; RAM &#x529F;&#x80FD;&#x975E;&#x5E38;&#x7B80;&#x5355;, &#x9002;&#x5408;&#x76F4;&#x63A5;&#x901A;&#x8FC7; RTL &#x5B9E;&#x73B0;.</li>
</ul>
<h5 id="ahbliteinterconnect">AHBlite_Interconnect</h5>
<ul>
<li>&#x8BBE;&#x6709; 1 &#x4E2A;&#x4E3B;&#x8BBE;&#x5907;&#x63A5;&#x53E3;&#x548C; 3 &#x4E2A;&#x4ECE;&#x8BBE;&#x5907;&#x63A5;&#x53E3;, &#x4E3B;&#x8BBE;&#x5907;&#x63A5;&#x53E3;&#x7528;&#x4E8E;&#x8FDE;&#x63A5; Cortex-M0, &#x4ECE;&#x8BBE;&#x5907;&#x63A5;&#x53E3; Port0 &#x7528;&#x4E8E;&#x8FDE;&#x63A5; BRAM, <font color="red">Port1 &#x548C; Port2 &#x5728;&#x672C;&#x5B9E;&#x9A8C;&#x4E2D;&#x6CA1;&#x6709;&#x88AB;&#x4F7F;&#x7528;&#x5230;.</font></li>
<li>&#x6240;&#x6709;&#x8BBE;&#x5907;&#x63A5;&#x53E3;&#x5747;&#x91C7;&#x7528; AHB &#x534F;&#x8BAE;&#x6807;&#x51C6;.</li>
</ul>
<h5 id="ahbliteblockram">AHBlite_Block_RAM</h5>
<p>&#x7531;&#x4E8E;&#x603B;&#x7EBF;&#x4E92;&#x8FDE;&#x63A5;&#x53E3;&#x90FD;&#x91C7;&#x7528; AHB &#x534F;&#x8BAE;&#x6807;&#x51C6;, &#x4E0D;&#x80FD;&#x76F4;&#x63A5;&#x4E0E; Block_RAM &#x8FDE;&#x63A5;, &#x56E0;&#x6B64;&#x9700;&#x8981;&#x672C;&#x6A21;&#x5757;&#x4F5C;&#x4E3A; RAM &#x63A5;&#x53E3;, &#x8D77;&#x5230;&#x6865;&#x63A5;&#x7684;&#x4F5C;&#x7528;.</p>
<h5 id="ahblitedecoder">AHBlite_Decoder</h5>
<ul>
<li>&#x5730;&#x5740;&#x8BD1;&#x7801;&#x662F;&#x603B;&#x7EBF;&#x4E92;&#x8FDE;&#x6A21;&#x5757;&#x5B9E;&#x73B0;&#x4ECE;&#x8BBE;&#x5907;&#x9009;&#x62E9;&#x7684;&#x5173;&#x952E;, &#x603B;&#x7EBF;&#x6839;&#x636E;&#x4E3A;&#x6BCF;&#x4E2A;&#x4ECE;&#x8BBE;&#x5907;&#x5212;&#x5206;&#x7684;&#x5730;&#x5740;&#x533A;&#x57DF;, &#x4EE5;&#x53CA;&#x5F53;&#x524D;&#x63A5;&#x6536;&#x5230;&#x7684;&#x6765;&#x81EA;&#x4E8E; CM0 &#x7684;&#x5730;&#x5740; (HADDR), &#x4F7F;&#x80FD;&#x5BF9;&#x5E94;&#x7684;&#x4ECE;&#x8BBE;&#x5907;. &#x5176;&#x672C;&#x8D28;&#x662F;&#x5BF9; HADDR &#x9AD8;&#x4F4D;&#x7684;&#x8BD1;&#x7801;.</li>
<li><font color="red">&#x6572;&#x9ED1;&#x677F;: &#x672C;&#x5B9E;&#x9A8C;&#x4E2D;&#x7684;&#x5730;&#x5740;&#x8BD1;&#x7801;&#x6A21;&#x5757;&#x5E94;&#x5F53;&#x91C7;&#x7528;&#x7EC4;&#x5408;&#x903B;&#x8F91;&#x5B9E;&#x73B0;, &#x5728;&#x7F16;&#x5199;&#x8BBE;&#x5907;&#x4F7F;&#x80FD;&#x6709;&#x5173;&#x7684;&#x4EE3;&#x7801;&#x65F6;, &#x5E94;&#x5F53;&#x6CE8;&#x610F;&#x4F7F;&#x7528; Port0_en &#x81F3; Port1_en &#x8FD9;&#x51E0;&#x4E2A; parameter, &#x4EE5;&#x4FDD;&#x8BC1;&#x53C2;&#x6570;&#x5316;&#x8BBE;&#x8BA1;, &#x8FD9;&#x5C31;&#x8981;&#x6C42;&#x5E94;&#x5F53;&#x6839;&#x636E;&#x4ECE;&#x8BBE;&#x5907;&#x63A5;&#x53E3;&#x7684;&#x4F7F;&#x7528;&#x60C5;&#x51B5;&#x5408;&#x7406;&#x5730;&#x4E3A; Port0_en &#x81F3; Port1_en &#x8D4B;&#x503C;. </font></li>
</ul>
<h5 id="ahbliteslavemux">AHBlite_SlaveMUX</h5>
<ul>
<li>&#x4E09;&#x4E2A;&#x4ECE;&#x8BBE;&#x5907;&#x8FD4;&#x56DE;&#x7684;&#x4FE1;&#x53F7; (&#x4F8B;&#x5982; HRDATA, HREADYOUT, HRESP) &#x8FDB;&#x884C;&#x591A;&#x8DEF;&#x9009;&#x62E9;&#x540E;&#x8FD4;&#x56DE;&#x81F3; CM0.</li>
<li>&#x5728;&#x672C;&#x5B9E;&#x9A8C;&#x4E2D;&#x5DF2;&#x7ECF;&#x7F16;&#x5199;&#x5B8C;&#x5584;, &#x53EF;&#x4EE5;&#x4E0D;&#x7528;&#x7BA1;.</li>
</ul>
<h5 id="cortexm0soc">CortexM0_SoC</h5>
<ul>
<li>&#x9876;&#x5C42;&#x6587;&#x4EF6;. &#x7528;&#x4E8E;&#x6BCF;&#x4E2A;&#x7CFB;&#x7EDF;&#x6A21;&#x5757;&#x7684;&#x4E92;&#x8FDE;.</li>
<li><font color="red">&#x6572;&#x9ED1;&#x677F;: &#x5728;&#x5BF9; AHBlite_Block_RAM &#x548C; AHBlite_Interconnect &#x7684; AHB &#x534F;&#x8BAE;&#x63A5;&#x53E3;&#x8FDB;&#x884C;&#x8FDE;&#x63A5;&#x65F6;, &#x53EA;&#x9700;&#x5C06;&#x540C;&#x540D;&#x4FE1;&#x53F7;&#x8FDE;&#x63A5;, &#x5E76;&#x6CE8;&#x610F;&#x4FE1;&#x53F7;&#x7684;&#x6765;&#x6E90;&#x548C;&#x65B9;&#x5411;.</font></li>
</ul>
<p>&#x4E3A;&#x4E86;&#x4E0D;&#x5F71;&#x54CD;&#x540E;&#x9762;&#x7684;&#x5B9E;&#x9A8C;, &#x8BF7;&#x53C2;&#x8003;&#x6807;&#x51C6;&#x7B54;&#x6848;:
<!-- --></p>
<div class="panel panel-success"><div class="panel-heading"><h5 class="panel-title" id="&#x4EE3;&#x7801;&#x4FEE;&#x6539;&#x65B9;&#x5F0F;"><i class="fa fa-lightbulb-o"></i> &#x4EE3;&#x7801;&#x4FEE;&#x6539;&#x65B9;&#x5F0F;</h5></div><div class="panel-body"><p>&#x5C06; &quot;/Task2/rtl/AHBlite_Decoder.v&quot; &#x4E2D;&#x7684;:</p><pre><code class="lang-verilog"><span class="hljs-comment">/*RAMCode enable parameter*/</span>
<span class="hljs-keyword">parameter</span> Port0_en = <span class="hljs-number">0</span>,
<span class="hljs-comment">/************************/</span>
</code></pre><p>&#x6539;&#x4E3A;:</p><pre><code class="lang-verilog"><span class="hljs-comment">/*RAMCode enable parameter*/</span>
<span class="hljs-keyword">parameter</span> Port0_en = <span class="hljs-number">1</span>,
<span class="hljs-comment">/************************/</span>
</code></pre><p>&#x7136;&#x540E;&#x5C06;:</p><pre><code class="lang-verilog"><span class="hljs-comment">//0x00000000-0x0000ffff</span>
<span class="hljs-comment">/*Insert RAMCODE decoder code there*/</span>
<span class="hljs-keyword">assign</span> P0_HSEL = <span class="hljs-number">1&apos;b0</span>;
<span class="hljs-comment">/***********************************/</span>
</code></pre><p>&#x6539;&#x4E3A;:</p><pre><code class="lang-verilog"><span class="hljs-comment">//0x00000000-0x0000ffff</span>
<span class="hljs-comment">/*Insert RAMCODE decoder code there*/</span>
<span class="hljs-keyword">assign</span> P0_HSEL = (HADDR[<span class="hljs-number">31</span>:<span class="hljs-number">16</span>] == <span class="hljs-number">16</span>&apos;h0000) ? Port0_en : <span class="hljs-number">1&apos;b0</span>; 
<span class="hljs-comment">/***********************************/</span>
</code></pre><p>&#x5C06; &quot;/Task2/rtl/CortexM0_SoC.v&quot; &#x4E2D;&#x7684;:</p><pre><code class="lang-verilog"><span class="hljs-comment">/* Connect to Interconnect Port 0 */</span>
.HCLK              (clk),
.HRESETn           (cpuresetn),
.HSEL              (<span class="hljs-comment">/*Port 0*/</span>),
.HADDR             (<span class="hljs-comment">/*Port 0*/</span>),
.HPROT             (<span class="hljs-comment">/*Port 0*/</span>),
.HSIZE             (<span class="hljs-comment">/*Port 0*/</span>),
.HTRANS            (<span class="hljs-comment">/*Port 0*/</span>),
.HWDATA            (<span class="hljs-comment">/*Port 0*/</span>),
.HWRITE            (<span class="hljs-comment">/*Port 0*/</span>),
.HRDATA            (<span class="hljs-comment">/*Port 0*/</span>),
.HREADY            (<span class="hljs-comment">/*Port 0*/</span>),
.HREADYOUT         (<span class="hljs-comment">/*Port 0*/</span>),
.HRESP             (<span class="hljs-comment">/*Port 0*/</span>),
.BRAM_WRADDR       (RAMCODE_WADDR),
.BRAM_RDADDR       (RAMCODE_RADDR),
.BRAM_RDATA        (RAMCODE_RDATA),
.BRAM_WDATA        (RAMCODE_WDATA),
.BRAM_WRITE        (RAMCODE_WRITE)
<span class="hljs-comment">/**********************************/</span>
</code></pre><p>&#x6539;&#x4E3A;:</p><pre><code class="lang-verilog"><span class="hljs-comment">/* Connect to Interconnect Port 0 */</span>
.HCLK              (clk),
.HRESETn           (cpuresetn),
.HSEL              (HSEL_P0),
.HADDR             (HADDR_P0),
.HPROT             (HPROT_P0),
.HSIZE             (HSIZE_P0),
.HTRANS            (HTRANS_P0),
.HWDATA            (HWDATA_P0),
.HWRITE            (HWRITE_P0),
.HRDATA            (HRDATA_P0),
.HREADY            (HREADY_P0),
.HREADYOUT         (HREADYOUT_P0),
.HRESP             (HRESP_P0),
.BRAM_WRADDR       (RAMCODE_WADDR),
.BRAM_RDADDR       (RAMCODE_RADDR),
.BRAM_RDATA        (RAMCODE_RDATA),
.BRAM_WDATA        (RAMCODE_WDATA),
.BRAM_WRITE        (RAMCODE_WRITE)
<span class="hljs-comment">/**********************************/</span>
</code></pre></div></div>
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